Typically, in a system or a circuit, a clock is used as a reference to match operation timing, or used to guarantee faster operation without error. When an external inputted clock is used inside the system or the circuit, time delay(or, clock skew) happens due to the internal circuit. Therefore, a DLL(Delay Locked Loop) is introduced to compensate such a time delay so that an internal clock can have same phase as the external clock.
The delay time between output data and the external clock is called as tAC. That is, it means time difference between the expected clock timing for data output and the actual clock timing for data output.
On the other hand, because the DLL is less affected by noise compared to a PLL(Phase Locked Loop), it is widely used for a synchronous semiconductor memory such as a DDR SDRAM(Double Data Rate Synchronous DRAM). Among some kinds of the DLL, a register controlled DLL is a most typically used DLL is.
FIG. 1 provides a block diagram of a register controlled DLL of a DDR SDRAM in prior art(see, Korean Patent publication No. 10-2993-0002130).
Referring to FIG. 1, the register controlled DLL comprises a first clock buffer 11, a second clock buffer 12, a clock divider 13, a first delay line 14, a second delay line 15, a third delay line 16, a shift register 17, a first DLL driver 20, a second DLL driver 21, a delay model 22, a phase comparator 19 and a shift controller 18. The first clock buffer 11 receives an inverted external clock/clk as its input to generate an internal clock fall_clk that is synchronized to the falling edge of the external clock clk. The second clock buffer 12 receives the external cock clk as its input to generate an internal clock rise_clk that is synchronized to the rising edge of the external clock clk. The clock divider 13 divides the internal clock rise_clk that is synchronized to the rising edge of the external clock clk by 1/n(here, n is a positive integer, typically 8) to output a delay monitoring clock dly_in and a reference clock ref. The first delay line 14 receives the internal clock fall_clk that is synchronized to the falling edge of the external clock clk. The second delay line 15 receives the internal clock rise_clk that is synchronized to the rising edge of the external clock clk. The third delay line 15 receives the delay monitoring clock dly_clk. The shift register 17 determines delay amounts for the first, the second and the third delay lines 14, 15, 16. The first DLL driver 20 drives the output ifclk of the first delay line 14 to generate a DLL clock fclk_dll. The second DLL driver drives the output irclk of the second delay line 15 to generate a DLL clock rclk_dll. The delay model 22 receives the output of the third delay line 16 to make the clock go through delay condition as same as the actual clock path. The phase comparator 19 compares the pahse of the output fbclk to that of the reference clock ref. The shift controller 18 controls shift direction of the shift register 17 in response to the control signal ctrl from the phase comparator 19.
First, the first clock buffer 11 generates the internal clock fall_clk that is synchronized to the falling edge of the external clock clk and the second clock buffer 12 generates the internal clkc rise_clk that is synchronized to the rising edge of the external clock clk. The clock divider 13 performs 1/n division on the internal clock rise_clk that is synchronized to the rising edge of the external clock clk to generate the clocks ref, dly_in that are synchronized to every n-th clock of the external clock clk. Because both of the reference clock ref and the delay monitoring clock dly_in are divided signals from the internal clock rise_clk that is synchronized to the rising edge of the external clock clk, they have pulse widths of one period tCK of the external clock clk. Also, the phase of the reference clock ref is different from that of the delay monitoring clock dly_in by 180 degrees.
During initial operation, the delay monitoring clock dly_in is outputted through only one unit delay device of the third delay line 16 of the delay monitor 10 and then passes through the delay model 22 to be outputted as a feedback clock fbclk. Here, the feedback clock fbclk is delayed by the delay time of the delay model 22 compared to the output clock of the third delay line 16.
On the other hand, the phase comparator 19 generates the control signal ctrl by comparing the rising edge of the reference clock ref to the rising edge of the feedback clock fbclk. The shift register 18 outputs a shift control signal SR, SL to control the shift direction of the shift register 17 in response to the control signal ctrl. The shift register 17 determines the delay amounts of the first, the second and the third delay lines 14, 15, 16 in response to the shift control signal SR, SL. That is, when the SR(Shift Right) signal is inputted, the register is shifted to the right. When the SL(shift Left) signal is inputted the register is shifted to the left. After that, while comparing the delay controlled feedback clock to the reference clock, it occurs delay locking at that moment when the two clocks have minimum jitter, in which the DLL clocks fclk_dll, rclk_dll have their phases as same as the external clock clk that is outputted from the first and the second DLL drivers 20, 21, respectively.
The conventional delay locked loop as described above does not use the internal clock rise_clk that is synchronized to the rising edge of the external clock clk but use the divided clock that is divided by the clock divider 13, as its input clock. The reason why it does so is benefit of reducing current that is spent to compare phases from reducing the number of comparisons of the phase comparator 19(as the clock is divided). Also, as the frequency of the external clock is raised due to increasing speed of the semiconductor memory, the divided clock is used because a more complicated control logic should be added to the shift comparator 19 to monitor the delay by using such a high frequency.
FIG. 2 is a circuit diagram of a ⅛ clock divider in prior art.
Referring to FIG. 2, the conventional ⅛ divider includes a first dividing stage 200, a second dividing stage 201, and a third dividing stage 202. The first dividing stage 200 receives the internal clock rise_clk that is synchronized to the rising edge of the input clock clk to generate a ½ divided clock A. The second dividing stage 201 receives the output clock of the first dividing stage 200 to generate a ¼ divided clock B. The third dividing stage 202 receives the output clock of the second dividing stage 201 to generate a ⅛ divided clock ref.
Here, each of the dividing stages 200, 201, 202 is constituted by a T-flip flop using a cross-coupled NAND latch. The ⅛ divided clock from the third dividing stage 202 is used as the reference clock ref and its inverted version is use as the monitoring clock dly_in.
FIG. 3 shows a waveform diagram for explaining operation of the circuit shown in FIG. 2.
Referring to FIG. 3, the first dividing stage 200 receives the output clock rise_clk having a clock period of tCK of the second clock buffer 12 as its input to generate the clock signal A having a clock period of 2 tCK. The second dividing stage 201 receives the output clock A of the first dividing stage 200 as its input to generate the ½ divided clock signal B. The clock signal B has a period of 4 tCK compared to the input clock rise_clk of the divider, which goes to a low level per 4 periods and stays for tCK. The third dividing stage 202 receives the output clock B of the second dividing stage 201 as its input to generate the ½ divided clock signal ref. The clock signal ref has a period of 8 tCK compared to the input clock rise_clk of the divider, which goes to a low level per 8 periods and stays for tCK.
On the other hand, when the clock period that is divided by the clock divider is fixed as described above, the tAC due to variation of process, temperature, voltage and etc. of the memory cannot be measured. The reference clock ref and the monitoring clock dly_in to optimize the tAC cannot be provided, either.
The problem mentioned above may happen all kinds of the delay locked loops that use the divider as well as the register controlled delay locked loop.